The present inventions relates to a semiconductor integrated circuit (semiconductor device) including electrically erasable and programmable non-volatile memory elements; and, more particularly, the invention relates to a technology which can be effectively applied to, for example, a microcomputer or a memory LSI in which non-volatile memory elements, which are capable of being mounted without adding a new process to an existing CMOS process and are formed using a single layer poly flash technology, are used for a fault recovery and the like.
A single layer poly flash technology constituting the memory cell of a non-volatile memory by a single layer poly silicon gate is disclosed in Japanese Patent Laid-Open No. 334190/1994 (which corresponds to U.S. Patent Publication No. 5,465,231), U.S. Patent Publication No. 5,440,159, U.S. Patent Publication No. 5,504,706, Japanese Patent Laid-Open No. 212-471/1992 (which corresponds to U.S. Patent Publication No. 5,457,335, 5,767,544 and 6,064,606), and “A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes”, IEEE Journal of Solid State Circuits, VOL. 29, NO. 3, March 1994, pp. 311-316. For example, in a non-volatile memory cell formed by a single layer poly flash technology disclosed in Japanese Patent Laid-Open No. 334190/1994, a first conductivity type MOS transistor is formed on a semiconductor substrate and a plate electrode formed in a second conductivity type well via an insulating layer, wherein the gate electrode of the MOS transistor and the plate electrode are connected to each other and function as a floating gate, and wherein the second conductivity type well functions as a control gate.
In Japanese Patent Laid-Open No. 212471/1992, there is also disclosed a technology for utilizing an electrically programmable non-volatile memory (EPROM) as a recovery circuit of a read only memory (ROM). Further, it is described in this publication that a non-volatile memory element having a first layer gate structure can also be used as an electrically programmable and erasable non-volatile memory element, in which a write operation is performed by hot carriers and an erase operation is performed by a tunnel current produced by applying a high voltage to a source or a drain, or the write and erase operations are performed by the tunnel current.
On the other hand, a technology for differentially utilizing two non-volatile memory elements from the viewpoint of preventing a malfunction is disclosed in Japanese Patent Laid-Open No. 163797/1992, Japanese Patent Laid-Open No. 263999/1989, Japanese Patent Laid-open No. 74392/1992, Japanese Patent Laid-Open No. 127478/1990, Japanese Patent Laid-Open No. 129091/1992, Japanese Patent Laid-Open No. 268180/1994, and U.S. Patent No.5,029,131. In a differential type memory cell structure, one non-volatile memory element is set in a writing state and the other non-volatile memory element is set in an erasing state, and signals read out in parallel from both the non-volatile memory elements are differentially amplified and the logic value of memory information is judged according to which output of the non-volatile memory elements in the writing state or in the erasing state becomes either an input to an inversion side or a non-inversion side.